In general, in order to erase a data stored on the flash EEPROM, a negative voltage is supplied to the gate electrode of the flash EEPROM cell.
In order to supply such a negative voltage, clock signals CLK1 and CLK2 are input to the clock signal generator 1 as shown in FIG. 1. Depending on the first and second clock signals CLK1 and CLK2 which is output from the clock signal generator 1, a first, second and third negative voltages VNQP, VINQP and VINQPB are generated at the charge pump 2. Each of the first and second negative voltages VLNQP and VINQPB is supplied to a first and second negative voltage drive circuits 3A and 3B, respectively. Each of the first and second output signals S1 and S2 of the first and second negative voltage drive circuits 3A and 3B is input to the gate electrodes of the pass transistors P1 and P2, respectively. The first negative voltage VNQP is supplied to the program gate PG of the flash EEPROM cell 4 depending on the drive of the pass transistors P1 and P2. The first and second negative voltage drive circuits 3A and 3B are substanially same in their constructions.
The present invention is directed to the negative voltage drive circuit 3 shown in FIG. 1.
The conventional negative voltage drive circuit will be explained by reference to FIG. 2. FIG. 2 illustrates a detailed circuit diagram of the first negative voltage drive circuit shown in FIG. 1.
A first clock signal CK1 is applied to the pumping capacitor M1 and a second clock signal CK2 is applied to the pumping capacitor M2. The first and second clock signals CK1 and CK2 are opposite in phase.
PMOS transistors P1 and P2, to which the first and second clock signals CK1 and CK2 via the pumping capacitors M1 and M2 are input, are alternately turned on and thus the negative voltage VINQP is sent to the output terminal Vout connected to the load capacitor CL.
As the pumping capacitor M1 is directly connected to the output terminal Vout, however, the voltage which is coupled by the pumping capacitors M1 and M2 varies based on the load. In addition, as the PMOS transistors P1 and P2 take the Body Effect, the threshold voltages of the PMOS transistors increase. If this threshold voltage is higher than the coupling voltage generated by the ratio of the pumping capacitors M1 and M2 and the load capacitor CL, the PMOS transistors P1 and P2 are no longer turned on. Therefore, as the output voltage of the charge pump is no longer generated, the output therefrom becomes saturated.
Also, if the capacity of the load capacitor CL is greater than that of the pumping capacitors M1 and M2 and also the Gamma Effect (.gamma. Effect) is great enough, the output therefrom will be saturated before it decreases to a given voltage. As a result, there is a problem in that the output voltage of such a circuit takes a lot of influence due to the load capacitance.
In addition, as the coupling voltage varies with the clock signals, there is a shortcoming that it takes a lot of influence based on the power supply voltage Vcc.